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STW5094ADT bảng dữ liệu(PDF) 9 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  18-bit Low Power Asynchronous Stereo Audio DAC with Integrated Power Amplifiers and Voice Codec
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STw5094A
2 DEVICE OPERATION
2.1 Power on Initialization, Software Reset
When power is first applied, the “power on reset” circuitry initializes STw5094A and puts it into the power
down state. All the Registers are initialized as indicated in the Control Register description section. All the
functions are disabled.
The registers can also be initialized to the default state by writing bit SRS (software reset) in CR21.
2.2 Power up
⁄ down control
It is recommended that all programmable functions (excluding the gain controls, bass-treble controls and
dynamic compression function) are set while the device is powered down. Power state control can then
be included in the last programming instruction (the power up bit PU is located in the last address register
(CR21) so that the multi-byte mode of the control interface can be easily used to program all the required
functions before power up).
When a power up command is given, all the circuits needed for the selected mode are activated (in Voice
mode the DX output will remain in the high impedance state until the second FS pulse after power up ar-
rives). A built-in power consumption management function keeps in power down the blocks that are not
needed by the selected operating mode.
2.3 Power down state
Following a period of activity, power down state may be reentered by writing 0 in bit PU in CR21. All the Control
Registers remain in their current state and can be changed by I2C control interface.
In addition to the power down instruction, the detection of absence of the current Master Clock (no transition
detected) automatically puts the device in power down state without setting bit PU. If transitions on the master
clock are detected the device is put again in power up.
2.4 Voice Transmit section
This section is active in Voice Mode. Voice Transmit analog preamplifier gain is designed in two stages to
enable gains up to 42.5 dB. Stage 1 provides a selectable 0 or 20 dB gain via bit PG in CR4. Stage 2 is a
programmable gain amplifier which provides from 0 to 22.5 dB of additional gain in 1.5dB step. It can be
programmed with bits TXA in CR4. Three microphone inputs are provided, two differential (MIC1P
⁄ N,
MIC2P
⁄ N) and one single ended (MIC3). They may also be used connect an auxiliary audio circuit. The
microphone input or Transmit Mute is selected with bits MS in CR4. In the Mute case, the analog transmit
signal is grounded. A separate MBIAS output can be used to bias a microphone (bit MB in CR4). An active
anti-alias filter then precedes the single bit
Σ∆ analog to digital converter that is followed by an 8th order
IIR digital TX channel filter. The TX channel filter is band-pass if the FS frequency is 8kHz and low-pass
if the FS frequency is 16kHz (bit VFS in CR0). A precision on chip voltage reference ensures accurate and
highly stable transmission levels. Any offset voltage arising in the analog blocks is cancelled by an internal
autozero circuit. Voice data is sent to the PCM I
⁄ F to be serially sent to DX output.
2.5 Voice Receive section
This section is active in Voice Mode. Voice Data coming from PCM I
⁄ F DR pin is sent to the 8th order
digital IIR RX channel filter. The filter can be selected to be band-pass or low-pass, with bit HPB in CR5,
when FS frequency is 8kHz, while it is always low-pass when FS frequency is 16kHz. The filter is followed
by a
Σ∆ digital to analog converter and a 3rd order switched-capacitor reconstruction filter. The Sidetone
can be summed to the received signal (bit SI in CR5) and its amplitude can be programmed with bits SA
in CR5.
2.6 Stereo Audio DAC section
This section is active in Audio Mode. The Left and Right Audio samples coming from the Audio Interface
are interpolated with an FIR filter and synchronized to the AMCK clock in order to feed the oversampled
multi-bit
Σ∆ modulator, the digital to analog converter is followed by a 3rd order switched-capacitor recon-
struction filter.


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