November 1991

7

Philips Semiconductors

Product specification

TSA5515T

READ mode:

R/W = 1 (see Table 2)

Data can be read out of the TSA5515T by setting the R/W

bit to 1. After the slave address has been recognized, the

TSA5515T generates an acknowledge pulse and the first

data byte (status word) is transferred on the SDA line

(MSB first). Data is valid on the SDA line during a high

position of the SCL clock signal.

A second data byte can be read out of the TSA5515T if the

processor generates an acknowledge on the SDA line.

End of transmission will occur if no acknowledge from the

processor occurs. The TSA5515T will then release the

data line to allow the processor to generate a STOP

condition.

below 3 V and at power-on. It is reset when an end of data

is detected by the TSA5515T (end of a READ sequence).

Control of the loop is made possible with the in-lock flag

FL, which indicates (FL = 1) when the loop is

phase-locked.

Table 2

Read data format

Notes

1. POR

power-on-reset flag. (POR = 1 on power-on)

2. FL

in-lock flag (FL = 1 when the loop is phase-locked).

MSB is transmitted first.

Address selection (see Table 3)

The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having several

synthesizers (up to 4) in one system. The relationship between MA1 and MA0 and the input voltage on AS input is given

in Table 3.

Table 3

Address selection

MSB

LSB

Address

11000

MA1

MA0

1

A

byte 1

Status byte

POR

FL

111111

−

byte 2

MA1

MA0

Voltage applied on AS pin

0

0

0

1

open

1

0

1

1