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TDA9964HL bảng dữ liệu(PDF) 7 Page - NXP Semiconductors |
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7 / 24 page  2000 May 02 7 Philips Semiconductors Objective specification 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9964 Digital inputs PINS: SHP, SHD AND CLK (REFERENCED TO DGND) VIL LOW-level input voltage 0 − 0.6 V VIH HIGH-level input voltage 2.2 − 5.5 V Ii input current 0 ≤ Vi ≤ 5.5 V −3 − +3 µA Zi input impedance fCLK =30MHz − 50 − k Ω Ci input capacitance fCLK =30MHz −− 2pF PINS: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK, VSYNC VIL LOW-level input voltage 0 − 0.6 V VIH HIGH-level input voltage 2.2 − 5.5 V Ii input current 0 ≤ Vi ≤ 5.5 V −2 − +2 µA Clamps GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS tW(clamp) clamp active pulse width in number of pixels PGA code = 255 for maximum 4 LSB error 12 −− pixels INPUT CLAMP (DRIVEN BY CLPDM) gm(CDS) CDS input clamp transconductance − 20 − mS Correlated Double Sampling (CDS) Vi(CDS)(p-p) maximum peak-to-peak CDS input amplitude (video signal) VCC = 2.85 V 650 −− mV VCC ≥ 3.0 V 800 −− mV Vreset(max) maximum CDS input reset pulse amplitude 500 −− mV Ii(IN) input current into pin IN at floating gate level tbf − tbf µA Ci input capacitance − 2 − pF tCDS(min) CDS control pulses minimum active time Vi(CDS)(p-p) = 800 mV black to white transition in 1 pixel with 99% Vi recovery − 8 − ns th(IN;SHP) CDS input hold time (pin IN) compared to control pulse SHP VCCA =VCCD = 3.0 V; Tamb =25 °C; see Figs 3 and 4 − 12 ns th(IN;SHD) CDS input hold time (pin IN) compared to control pulse SHD VCCA =VCCD = 3.0 V; Tamb =25 °C; see Figs 3 and 4 − 12 ns Amplifier DRPGA PGA dynamic range − 24 − dB ∆GPGA PGA gain step 0.08 0.10 0.12 dB Analog-to-Digital Converter (ADC) DNL differential non linearity fpix = 30 MHz; ramp input −±0.5 ±0.9 LSB SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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