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STK11C88-3NF45I bảng dữ liệu(PDF) 3 Page - Simtek Corporation

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STK11C88-3
March 2006
3
Document Control # ML0013 rev 0.2
SRAM READ CYCLES #1 & #2
(VCC = 3.0V-3.6V)
Note f:
W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g:
I/O state assumes E and G < VIL and W > VIH; device is continuously selected.
Note h:
Measured
± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
SRAM READ CYCLE #2: E Controlledf
NO.
SYMBOLS
PARAMETER
STK11C88-3-35
STK11C88-3-45
STK11C88-3-55
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
tELQV
tACS
Chip Enable Access Time
35
45
55
ns
2
tAVAV
f
tRC
Read Cycle Time
35
45
55
ns
3
tAVQV
g
tAA
Address Access Time
35
45
55
ns
4
tGLQV
tOE
Output Enable to Data Valid
15
20
25
ns
5
tAXQX
g
tOH
Output Hold after Address Change
5
5
5
ns
6
tELQX
tLZ
Chip Enable to Output Active
5
5
5
ns
7
tEHQZ
h
tHZ
Chip Disable to Output Inactive
13
15
20
ns
8
tGLQX
tOLZ
Output Enable to Output Active
0
0
0
ns
9
tGHQZ
h
tOHZ
Output Disable to Output Inactive
13
15
20
ns
10
tELICCH
e
tPA
Chip Enable to Power Active
0
0
0
ns
11
tEHICCL
d, e
tPS
Chip Disable to Power Standby
35
45
55
ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALID
8
tGLQX
4
tGLQV
DQ (DATA
E
ADDRESS
2
tAVAV
G
ICC
ACTIVE
1
tELQV
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ


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