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TDA1313 bảng dữ liệu(PDF) 5 Page - NXP Semiconductors |
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5 / 15 page July 1993 5 Philips Semiconductors Objective specification Stereo continuous calibration DAC (CC-DAC) TDA1313; TDA1313T PINNING SYMBOL PIN DESCRIPTION LRSEL/RSI 1 left/right select; right serial input SI/LSI 2 serial input; left serial input 4/8FSSEL 3 4/8 oversampling select VREF 4 reference voltage output VSSO 5 operational amplifier ground VDDO 6 operational amplifier supply voltage RIN 7 right analog input ROUT 8 right analog output LOUT 9 left analog output LIN 10 left analog input VDDA 11 analog supply voltage VSSA 12 analog ground VSSD 13 digital ground VDDD 14 digital supply voltage WS 15 word select BCK 16 bit clock input Fig.2 Pin configuration. handbook, halfpage TDA1313 TDA1313T MGE229 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 LRSEL/RSI SI/LSI 4/8FSSEL VREF VSSO VDDO RIN ROUT LOUT LIN VDDA VSSA VSSD VDDD WS BCK FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value IREF, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the IO terminal. In the TDA1313; 1313T, 32 current sources and one spare current source are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is connected to an 11-bit binary current devider which consists of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed by switching only the LSB currents. The TDA1313; T (CC-DAC) accepts serial input data format of 16 bit word length. The most significant bit (bit 1) must always be first. The timing is illustrated in Fig.4 and the input data formats are illustrated in Figs 5 and 6. Data is placed in the right and left input registers (Fig.1). The data in the input registers is simultaneously latched to the output registers which control the bit switches. VREF and VFS are proportional to VDD. Where: VDD1/VDD2 = VFS1/V = VREF1/VREF2 |
Số phần tương tự - TDA1313 |
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Mô tả tương tự - TDA1313 |
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