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STR912FAW42X6 bảng dữ liệu(PDF) 11 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  ARM966E-S??16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STR912FAW42X6 bảng dữ liệu(HTML) 11 Page - STMicroelectronics

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STR91xFA
Functional overview
11/78
Flash memories are programmed half-word (16 bits) at a time, but are erased by sector or by
full array.
2.7.1
Primary Flash memory
Using the STR91xFA device configuration software tool and 3rd party Integrated Developer
Environments, it is possible to specify that the primary Flash memory is the default memory
from which the CPU boots at reset, or otherwise specify that the secondary Flash memory is
the default boot memory. This choice of boot memory is non-volatile and stored in a location
that can be programmed and changed only by JTAG In-System Programming. See Section 5:
Memory mapping, for more detail.
The primary Flash memory has equal length 64K byte sectors. Devices with 256 Kbytes of
primary Flash have four sectors and 512K devices have eight sectors.
2.7.2
Secondary Flash memory
The smaller of the two Flash memories can be used to implement a bootloader, capable of
storing code to perform robust In-Application Programming (IAP) of the primary Flash memory.
The CPU executes code from the secondary Flash, while updating code in the primary Flash
memory. New code for the primary Flash memory can be downloaded over any of the
interfaces on the STR91xFA (USB, Ethernet, CAN, UART, etc.)
Additionally, the Secondary Flash memory may also be used to store small data sets by
emulating EEPROM though firmware, eliminating the need for external EEPROM memories.
This raises the data security level because passcodes and other sensitive information can be
securely locked inside the STR91xFA device.
The secondary Flash memory is 32 Kbytes and has four equal length sectors of 8 Kbytes each.
Both the primary Flash memory and the secondary Flash memory can be programmed with
code and/or data using the JTAG In-System Programming (ISP) channel, totally independent of
the CPU. This is excellent for iterative code development and for manufacturing.
2.8
One-time-programmable (OTP) memory
There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory
calibration constants, or other permanent data constants. These OTP data bytes can be
programmed only one time through either the JTAG interface or by the CPU, and these bytes
can never be altered afterwards. As an option, a “lock bit” can be set by the JTAG interface or
the CPU which will block any further writing to the this OTP area. The “lock bit” itself is also
OTP. If the OTP array is unlocked, it is always possible to go back and write to an OTP byte
location that has not been previously written, but it is never possible to change an OTP byte
location if any one bit of that particular byte has been written before. The last two OTP bytes are
reserved for the STR91xFA product ID and revision level.
2.8.1
Product ID and revision level
OTP bytes 31 and 30 are programmed at ST factory before shipment and may be read by
firmware to determine the STR91xFA product type and silicon revision so it can optionally take
action based on the silicon on which it is running. Byte 31 contains the the major family
identifier of "9" (for STR9) in the high-nibble location, and the minor family identifier in the low-
nibble location. Today the low-nibble contains "1", but future family members may have other


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