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ST78C36CJ44 bảng dữ liệu(PDF) 8 Page - Exar Corporation |
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ST78C36CJ44 bảng dữ liệu(HTML) 8 Page - Exar Corporation |
8 / 28 page ST78C36/36A xr ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO REV. 5.0.2 8 Cnfg-A Bit-2: When transmitting, there is 1 byte waiting to be transmitted that does not affect FIFO-F. Cnfg-A Bit-3: Reserved, logic zero. Cnfg-A Bits 6-4: Indicates PWord = 1 byte (8-bit implementation). Cnfg-A Bit-7: Indicates ECP interrupts are pulsed. 3.11 CONFIGURATION REGISTER B ( Cnfg-B ) This register is available in ECR mode 111 only, and returns bits 0-5 as logic zero for the ST78C36CJ44. The ST78C36CQ64 will allow programmed selection of the Interrupt and DMA channels after a system RESET state of 001011 (bits 0-5). Cnfg-B Bits 2-0: With bit 2 forced low, select an 8-bit DMA channel per the following table: Cnfg-B Bits 5-3: Select an IRQ channel per the following table: Cnfg-B Bit-6: Returns the true value of the selected IRQ pad. Cnfg-B Bit-7: Indicates RLE compression is not supported. TABLE 1: DMA CHANNEL SELECTION: CNFG-B BITS[2:0] WRITE TO FIFO READ FROM FIFO DMA CHANNEL X00 000 3 X01 001 1 X10 010 2 X11 011 3 (Default) TABLE 2: IRQ SELECTION: CNFG-B BITS[5:3] WRITE TO FIFO READ FROM FIFO IRQ 000 001 7 001 001 7 (Default) 010 010 9 011 001 7 100 001 7 101 001 7 110 001 7 111 111 5 |
Số phần tương tự - ST78C36CJ44 |
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Mô tả tương tự - ST78C36CJ44 |
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