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MCF5328CVM240 bảng dữ liệu(PDF) 33 Page - Freescale Semiconductor, Inc |
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MCF5328CVM240 bảng dữ liệu(HTML) 33 Page - Freescale Semiconductor, Inc |
33 / 48 page Electrical Characteristics MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 33 5.11 USB On-The-Go The MCF5329 device is compliant with industry standard USB 2.0 specification. 5.12 ULPI Timing Specification Control and data timing requirements for the ULPI pins are given in Table 18. These timings apply in synchronous mode only. All timings are measured with either a 60 MHz input clock from the USB_CLKIN pin. The USB_CLKIN needs to maintain a 50% duty cycle. Control signals and 8-bit data are always clocked on the rising edge. The ULPI interface on the MCF5329 processor is compliant with the industry standard definition. Figure 19. ULPI Timing Diagram 5.13 SSI Timing Specifications This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync (SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below. Table 18. ULPI Interface Timing Parameter Symbol Min Max Units Setup time (control in, 8-bit data in) TSC, TSD — 3.0 ns Hold time (control in, 8-bit data in) THC, THD −1.5 — ns Output delay (control out, 8-bit data out) TDC, TDD — 6.0 ns Table 19. SSI Timing – Master Modes1 Num Description Symbol Min Max Units S1 SSI_MCLK cycle time2 tMCLK 8 × t SYS —ns S2 SSI_MCLK pulse width high / low 45% 55% tMCLK S3 SSI_BCLK cycle time3 tBCLK 8 × t SYS —ns S4 SSI_BCLK pulse width 45% 55% tBCLK S5 SSI_BCLK to SSI_FS output valid — 15 ns TSC THC TSD TDC TDD ULPI_CLK ULPI_STP ULPI_DATA ULPI_DIR/ULPI_NXT ULPI_DATA THD (Output) (Input) (Input-8bit) (Output-8bit) |
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