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MCF5327 bảng dữ liệu(PDF) 34 Page - Freescale Semiconductor, Inc |
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MCF5327 bảng dữ liệu(HTML) 34 Page - Freescale Semiconductor, Inc |
34 / 48 page MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4 Electrical Characteristics Freescale Semiconductor 34 S6 SSI_BCLK to SSI_FS output invalid -2 — ns S7 SSI_BCLK to SSI_TXD valid — 15 ns S8 SSI_BCLK to SSI_TXD invalid / high impedence -4 — ns S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 15 — ns S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 — ns 1 All timings specified with a capactive load of 25pF. 2 SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK). 3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not exceed 4 x fSYS. Table 20. SSI Timing – Slave Modes1 1 All timings specified with a capactive load of 25pF. Num Description Symbol Min Max Units S11 SSI_BCLK cycle time tBCLK 8 × t SYS —ns S12 SSI_BCLK pulse width high/low 45% 55% tBCLK S13 SSI_FS input setup before SSI_BCLK 10 — ns S14 SSI_FS input hold after SSI_BCLK 3 — ns S15 SSI_BCLK to SSI_TXD/SSI_FS output valid — 15 ns S16 SSI_BCLK to SSI_TXD/SSI_FS output invalid/high impedence -2 — ns S17 SSI_RXD setup before SSI_BCLK 10 — ns S18 SSI_RXD hold after SSI_BCLK 3 — ns Table 19. SSI Timing – Master Modes1 (continued) Num Description Symbol Min Max Units |
Số phần tương tự - MCF5327 |
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Mô tả tương tự - MCF5327 |
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