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MCF5327 bảng dữ liệu(PDF) 23 Page - Freescale Semiconductor, Inc |
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MCF5327 bảng dữ liệu(HTML) 23 Page - Freescale Semiconductor, Inc |
23 / 48 page Electrical Characteristics MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4 Freescale Semiconductor 23 Figure 8. FlexBus Write Timing 5.7 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. 5.7.1 SDR SDRAM AC Timing Characteristics The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS signal and its usage. Table 10. SDR Timing Specifications Symbol Characteristic Symbol Min Max Unit • Frequency of Operation1 • TBD 80 MHz SD1 Clock Period2 tSDCK 12.5 TBD ns SD3 Pulse Width High3 tSDCKH 0.45 0.55 SD_CLK SD4 Pulse Width Low4 tSDCKH 0.45 0.55 SD_CLK SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid tSDCHACV — 0.5 × SD_CLK +1.0 ns SD6 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold tSDCHACI 2.0 — ns SD7 SD_SDR_DQS Output Valid5 tDQSOV — Self timed ns SD8 SD_DQS[3:0] input setup relative to SD_CLK6 tDQVSDCH 0.25 × SD_CLK 0.40 × SD_CLK ns FB_CLK FB_R/W FB_TS FB_OE S0 S2 S3 DATA S1 ADDR[31:X] FB_A[23:0] FB_D[31:X] ADDR[23:0] FB_CSn, FB_BE/BWEn FB_TA FB3 FB1 FB2 FB7 FB6 |
Số phần tương tự - MCF5327 |
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Mô tả tương tự - MCF5327 |
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