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MCF5232CAB80 bảng dữ liệu(PDF) 10 Page - Freescale Semiconductor, Inc

tên linh kiện MCF5232CAB80
Giải thích chi tiết về linh kiện  Integrated Microprocessor Hardware Specification
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MCF523x Integrated Microprocessor Hardware Specification, Rev. 2
Design Recommendations
Freescale Semiconductor
10
5.2
Power Supply
•33
µF, 0.1 µF, and 0.01 µF across each power supply
5.2.1
Supply Voltage Sequencing and Separation Cautions
Figure 1 shows situations in sequencing the I/O VDD (OVDD), PLL VDD (PLLVDD), and Core VDD (VDD).
OVDD is specified relative to VDD.
Figure 1. Supply Voltage Sequencing and Separation Cautions
5.2.1.1
Power Up Sequence
If OVDD are powered up with VDD at 0 V, then the sense circuits in the I/O pads will cause all pad output
drivers connected to the OVDD to be in a high impedance state. There is no limit on how long after OVDD
powers up before VDD must powered up. VDD should not lead the OVDD or PLLVDD by more than 0.4 V
during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times
on the power supplies should be slower than 1
µs to avoid turning on the internal ESD protection clamp
diodes.
The recommended power up sequence is as follows:
1. Use 1
µs or slower rise time for all supplies.
2. VDD/PLLVDD and OVDD should track up to 0.9 V, then separate for the completion of ramps with
OVDD going to the higher external voltages. One way to accomplish this is to use a low drop-out
voltage regulator.
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
Notes:
VDD should not exceed OVDD or PLLVDD by more than 0.4 V
at any time, including power-up.
Recommended that VDD/PLLVDD should track OVDD up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
1.
2.
3.
4.
VDD, PLLVDD
OVDD


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