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MCF5208 bảng dữ liệu(PDF) 22 Page - Freescale Semiconductor, Inc |
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MCF5208 bảng dữ liệu(HTML) 22 Page - Freescale Semiconductor, Inc |
22 / 46 page MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 1 Electrical Characteristics Freescale Semiconductor 22 Figure 11. System PLL VDD Power Filter 5.4.2 Supply Voltage Sequencing and Separation Cautions The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD. 5.4.2.1 Power Up Sequence If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must power up. IVDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on the internal ESD protection clamp diodes. 5.4.2.2 Power Down Sequence If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there is an undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is: 1. Drop IVDD/PLLVDD to 0 V. 2. Drop EVDD/SDVDD supplies. Board VDD 10 Ω 0.1 µF PLL VDD Pin 10 µF GND |
Số phần tương tự - MCF5208_07 |
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Mô tả tương tự - MCF5208_07 |
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