công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MCZ33989EGR2 bảng dữ liệu(PDF) 3 Page - Freescale Semiconductor, Inc |
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MCZ33989EGR2 bảng dữ liệu(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 66 page Analog Integrated Circuit Device Data Freescale Semiconductor 3 33989 PIN CONNECTIONS PIN CONNECTIONS Figure 3. 33989 Pin Connections Table 1. 33989 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 18. Pin Number Pin Name Pin Function Formal Name Definition 1 RX Output Receive Data CAN bus receive data output pin. 2 TX Input Transmit Data CAN bus transmit data input pin. 3 VDD1 Power Output Voltage Digital Drain One 5.0 V regulator output pin. Supply pin for the MCU. 4 RST Output Reset This is the device reset output pin whose main function is to reset the MCU. This pin has an internal pullup current source to VDD. 5 INT Output Interrupt This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. 6–9 20–23 GND Ground Ground These device ground pins are internally connected to the package lead frame to provide a 33989-to-PCB thermal path. 10 V2 Input Voltage Source Two Sense input for the V2 regulator using an external series pass transistor. V2 is also the internal supply for the CAN transceiver. 11 V2CTRL Power Output Voltage Control Output drive source for the V2 regulator connected to the external series pass transistor. 12 VSUP Power Voltage Supply Supply input pin for the 33989. 13 HS1 Output High Side One Output of the internal high-side switch. The output current is internally limited to 150 mA. 14–17 L0:L3 Input Level 0: 3 Inputs from external switches or from logic circuitry. 22 CANH Output CAN High CAN high output pin. 23 CANL Output CAN Low CAN low output pin. 24 SCLK Input System Clock Clock input pin for the Serial Peripheral Interface (SPI). 25 MISO Output Master In/Slave Out SPI data sent to the MCU by the 33989. When CS is HIGH, the pin is in the high-impedance state. 26 MOSI Input Master Out/Slave In SPI data received by the 33989. 27 CS Input Chip Select The CS input pin is used with the SPI bus to select the 33989. 28 WD Output Watch Dog The WD output pin is asserted LOW if the software watchdog is not correctly triggered. WD MISO SCLK GND GND GND GND CANL CANH L3 L2 L1 CS MOSI RX RST INT GND GND GND GND V2 V2CTRL VSUP HS1 L0 TX VDD1 4 5 6 7 8 9 10 11 12 13 14 2 3 28 25 24 23 22 21 20 19 18 17 16 15 27 26 1 |
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Mô tả tương tự - MCZ33989EGR2 |
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