AD7840

REV. B

–9–

Figure 11. AD7840 Dynamic Performance Test Circuit

The digitizer sampling is synchronized with the AD7840 update

rate to ease FFT calculations. The digitizer samples the

AD7840 after the output has settled to its new value. Therefore,

if the digitizer was to sample the output directly it would effec-

tively be sampling a dc value each time. As a result, the dynamic

performance of the AD7840 would not be measured correctly.

Using the digitizer directly on the AD7840 output would give

better results than the actual performance of the AD7840. Us-

ing a filter between the DAC and the digitizer means that the

digitizer samples a continuously moving signal and the true dy-

namic performance of the AD7840 is measured.

Some applications will require improved performance versus fre-

quency from the AD7840. In these applications, a simple

sample-and-hold circuit such as that outlined in Figure 12 will

extend the very good performance of the AD7840 to 20 kHz.

Figure 12. Sample-and-Hold Circuit

Other applications will already have an inherent sample-and-

hold function following the AD7840. An example of this type of

application is driving a switched-capacitor filter where the up-

dating of the DAC is synchronized with the switched-capacitor

filter. This inherent sample-and-hold function also extends the

frequency range performance of the AD7840.

Performance versus Frequency

The typical performance plots of Figures 13 and 14 show the

AD7840’s performance over a wide range of input frequencies

at an update rate of 100 kHz. The plot of Figure 13 is without a

sample-and-hold on the AD7840 output while the plot of Figure

14 is generated with the sample-and-hold circuit of Figure 12 on

the output.

Figure 13. Performance vs. Frequency

(No Sample-and-Hold)

Figure 14. Performance vs. Frequency

(with Sample-and-Hold)