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MC100EPT25 bảng dữ liệu(PDF) 7 Page - ON Semiconductor |
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MC100EPT25 bảng dữ liệu(HTML) 7 Page - ON Semiconductor |
7 / 8 page TND301 http://onsemi.com 7 The Challenges: We Have a Better Solution Clock Management systems require the clocks to have low jitter and low skew. ECL logic provides less jitter and skew with a higher operating frequency than other technologies. ECL logic technology offers a number of advantages over CMOS, LVDS, and TTL in reducing clock errors caused by jitter and skew. ECL devices have 1 ps jitter and 25 ps skew compared to 15 ps jitter and 100 ps skew for LVDS and CMOS devices. (See Figure 11 and Figure 12). The frequency of ECL logic is 3 Ghz maximum frequency compared to 300 Mhz maximum frequency for LVDS and CMOS logic (see Figure 13). The rise and fall times of clock signals is very critical for edge placement. ECL logic provides rise and fall times of 100 ps compared to rise and fall times of 800 ps for LVDS and CMOS logic (see Figure 14). ECL logic technologies offer a number of advantages for reducing the noise due to crosstalk and signal mismatch on the backplane over CMOS, LVDS, and TTL technologies. ECL signals are differential signals and can be individually terminated to match the transmission impedance of the backplane ECL signals have adequate current (50 mA) to drive a backplane and can deliver signals with maximum frequencies of 3 Ghz. ECL peak–to–peak output signals of 800 mV provide a good signal–to–noise ratio and excellent EMI characteristics. 100 10 1 1000 100 2002 5 0 Figure 11. Standard I/O rms Jitter Figure 12. Standard I/O Skew 45 40 35 30 25 20 15 10 0 Figure 13. Standard I/O Fmax Figure 14. Standard Rise/Fall Time Comparisons 25 1000 10 1 10000 ECL 10 15 20 2003 2001 2000 LVDS CMOS 2002 2003 2001 2000 ECL LVDS CMOS 2002 2003 2001 2000 5 2002 2003 2001 2000 ECL LVDS CMOS ECL/PECL LVDS CMOS |
Số phần tương tự - MC100EPT25 |
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Mô tả tương tự - MC100EPT25 |
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