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MC9S08GB60 bảng dữ liệu(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 290 page  MC9S08GB/GT Data Sheet, Rev. 2.3 4 Freescale Semiconductor Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. This product incorporates SuperFlash® technology licensed from SST. Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2004. All rights reserved. Revision Number Revision Date Description of Changes 1.0 4/25/2003 Initial release 1.1 Electricals change, appendix A only 1.2 Electricals change, appendix A only 1.3 10/2/2003 Added module version table; clarifications 1.4 10/29/2003 Fixed typos and made corrections and clarifications 1.5 11/12/2003 Added 1-MHz IDD values to Electricals, appendix A 2 2/10/2004 Changed format of register names to enable reuse of code (from SCIBD to SCI1BD, even when only one instance of a module on a chip) Added new device: MC9S08GT16 to book. Added new 48-pin QFN package to book. BKGDPE description in Section 5 — changed PTD0 to PTG0. Changed typo in CPU section that listed MOV instruction as being 6 cycles instead of 5 (Table 8-2). 2.2 9/2/2004 Format to Freescale look-and-feel; Clarified RTI clock sources and other changes in Chapter 5; updated ICG initialization examples; expanded descriptions of LOLS and LOCS bits in ICGS1; updated ICG electricals Table A-9 and added a figure 2.3 12/01/2004 Minor changes to Table 7-4, Table 7-5, Table A-9; Clarifications in Section 11.10.6, “SCI x Control Register 3 (SCIxC3)”, Section 11.7, “Interrupts and Status Flags”, Section 11.8.1, “8- and 9-Bit Data Modes”, PTG availability in 48-pin package (see Table 2-2) |
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