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ADATE207BBPZ bảng dữ liệu(PDF) 9 Page - Analog Devices |
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ADATE207BBPZ bảng dữ liệu(HTML) 9 Page - Analog Devices |
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9 / 36 page  ADATE207 Rev. 0 | Page 9 of 36 Pin No. Mnemonic Input/Output1 Type Description G20 DR_EN_CH3_N D, O Differential open-drain Inverted DCL Drive Enable Signal for Channel 3. L20 LJ_CLK_P D, I Differential input Noninverted Low Jitter Clock Input. This pin can be multiplexed onto DR_DATA outputs for Channel 2 and Channel 3. K19 LJ_CLK_N D, I Differential Input Inverted Low Jitter Clock Input. This pin can be multiplexed onto DR_DATA outputs for Channel 2 and Channel 3. M3 COMP_H_CH0_P D, I Differential input terminated Noninverted DCL High Comparator Signal for Channel 0. Differential signal is Logic 1 when the DUT output is higher than VOH. M2 COMP_H_CH0_N D, I Differential input terminated Inverted DCL High Comparator Signal for Channel 0. J4 COMP_H_CH1_P D, I Differential input terminated Noninverted DCL High Comparator Signal for Channel 1. Differential signal is Logic 1 when the DUT output is higher than VOH. J3 COMP_H_CH1_N D, I Differential input terminated Inverted DCL High Comparator Signal for Channel 1. M18 COMP_H_CH2_P D, I Differential input terminated Noninverted DCL High Comparator Signal for Channel 2. Differential signal is Logic 1 when the DUT output is higher than VOH. M19 COMP_H_CH2_N D, I Differential input terminated Inverted DCL High Comparator Signal for Channel 2. J17 COMP_H_CH3_P D, I Differential input terminated Noninverted DCL High Comparator Signal for Channel 3. Differential signal is Logic 1 when the DUT output is higher than VOH. J18 COMP_H_CH3_N D, I Differential input terminated Inverted DCL High Comparator Signal for Channel 3. L3 COMP_L_CH0_P D, I Differential input terminated Noninverted DCL Low Comparator Signal for Channel 0. Differential signal is Logic 1 when the DUT output is higher than VOL. L4 COMP_L_CH0_N D, I Differential input terminated Inverted Low Comparator Signal for Channel 0. H1 COMP_L_CH1_P D, I Differential input terminated Noninverted DCL Low Comparator Signal for Channel 1. Differential signal is Logic 1 when the DUT output is higher than VOL. J2 COMP_L_CH1_N D, I Differential input terminated Inverted Low Comparator Signal for Channel 1. L18 COMP_L_CH2_P D, I Differential input terminated Noninverted DCL Low Comparator Signal for Channel 2. Differential signal is Logic 1 when the DUT output is higher than VOL. L17 COMP_L_CH2_N D, I Differential Input terminated Inverted Low Comparator Signal for Channel 2. H20 COMP_L_CH3_P D, I Differential input terminated Noninverted DCL Low Comparator Signal for Channel 3. Differential signal is Logic 1 when the DUT output is higher than VOL. J19 COMP_L_CH3_N D, I Differential input terminated Inverted Low Comparator Signal for Channel 3. M1 COMP_L_CH0_T A, I, O Analog Center Tap. Center tap of two 50 Ω resistor terminations for the low comparator differential inputs of Channel 0. |
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