© Freescale Semiconductor, Inc., 2005, 2006, 2007. All rights reserved.

Freescale Semiconductor

Data Sheet: Technical Data

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its

products.

Document Number: MCF5251

Rev. 2.2, 04/2007

MCF5251

Package Information

MAPBGA–225

Ordering Information: See Table 1 on page 2

1

Introduction

This document provides an overview of the MCF5251

ColdFire processor and general descriptions of the

MCF5251 features and modules. Also provided are

electrical specifications, pin assignments, and package

functional characteristics, refer to the MCF5251

Reference Manual (MCF5251RM).

The MCF5251 is a system controller/decoder for

compressed audio music players addressing both

portable and automotive solutions supporting CD, HDD

and USB based systems. The 32-bit ColdFire core with

enhanced multiply and accumulate (eMAC) unit

provides optimum performance and code density for the

combination of control code and signal processing

required for compressed audio decode, file management,

and system control.

The MCF5251 is a general purpose system controller

with over 125 Dhrystone 2.1 MIPS @ 140 MHz

performance. The integrated peripherals and EMAC

allow the MCF5251 to replace both the microcontroller

Microprocessor Data

Sheet

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Orderable Part Numbers . . . . . . . . . . . . . . 2

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 3

2 Functional Description . . . . . . . . . . . . . . . . . . . 4

2.1 Version 2 ColdFire Core . . . . . . . . . . . . . . . 4

2.2 Module Inventory . . . . . . . . . . . . . . . . . . . . 4

3 Signal Description . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical Specifications . . . . . . . . . . . . . . . . . 11

4.1 SDRAM Bus Timing . . . . . . . . . . . . . . . . . 14

4.2 SPDIF Timing . . . . . . . . . . . . . . . . . . . . . . 15

4.3 Serial Audio Interface Timing . . . . . . . . . . 16

4.4 DDATA/PST/PSTCLK Debug Interface . . 16

4.5 BDM and JTAG Timing . . . . . . . . . . . . . . 16

5 Package Information and Pinout . . . . . . . . . . 18

5.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . 18

5.2 Package Drawing . . . . . . . . . . . . . . . . . . . 24

6 Product Documentation . . . . . . . . . . . . . . . . . 31

6.1 Revision History . . . . . . . . . . . . . . . . . . . . 31