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MCF5251 bảng dữ liệu(PDF) 5 Page - Freescale Semiconductor, Inc |
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MCF5251 bảng dữ liệu(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 32 page Functional Description MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2.2 Freescale Semiconductor 5 GPIO General Purpose I/O Interface System integration GPIO signals are multiplexed with various other signals. GPT General Timer Module Timer peripheral The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer. IDE Integrated Drive Electronics Connectivity peripheral The IDE hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent SDRAM and Flash accesses from propagating to the IDE bus. INC Instruction Cache Core The instruction cache improves system performance by providing cached instructions to the execution unit in a single clock cycle. I2C Inter IC Communication Module Connectivity peripheral The two-wire I2C bus interfaces, compliant with the Philips I2C bus standard, are bidirectional serial buses that exchange data between devices. SRAM Internal 128-KB SRAM Internal memory The 128-Kbyte on-chip SRAM is split over two banks, SRAM0 (64K) and SRAM1 (64K). It provides single clock-cycle access for the ColdFire core. LIN Internal Voltage Regulator Linear regulator An internal 1.2 V regulator is used to supply the CPU and PLL sections of the MCF5251, reducing the number of external components required and allowing operation from a single supply rail, typically 3.3 volts. JTAG Joint Test Action Group Test and debug To help with system diagnostics and manufacturing testing, the MCF5251 includes dedicated user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. QSPI Queued Serial Peripheral Interface Connectivity Interface The QSPI module provides a serial peripheral interface with queued transfer capability. RTC Real-Time Clock Timer Peripheral The RTC is a clock that keeps track of the current time even if the clock is turned off. BDM Background Debug Interface Test and debug A background-debug mode (BDM) interface provides system debug. SDRAMC Synchronous DRAM Memory Controller Peripheral Interface The SDRAM controller provides a glueless interface for one bank of SDRAM, and can address up to 32MB. The controller supports a 16-bit data bus. The controller operates in page mode, non-page mode, and burst-page mode and supports SDRAMs. SIM System Integration Module System Integration The SIM provides overall control of the internal and external buses and serves as the interface between the ColdFire core and the internal peripherals or external devices. The SIM is responsible for the two interrupt controllers (setting priorities and levels). And it also configures the GPIO ports. PLL System Oscillator and Phase Lock Loop System Clocking The oscillator operates from an external crystal connected across CRIN and CROUT. The circuit can also operate from an external clock connected to CRIN. The on-chip programmable PLL, which generates the processor clock, allows the use of almost any low frequency external clock (5–35 MHz). Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name Functional Grouping Brief Description |
Số phần tương tự - MCF5251_07 |
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Mô tả tương tự - MCF5251_07 |
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