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ST92124JDV1TC bảng dữ liệu(PDF) 45 Page - STMicroelectronics |
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45 / 429 page 45/429 ST92F124/F150/F250 - DEVICE ARCHITECTURE ADDRESS SPACE EXTENSION (Cont’d) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program mem- ory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ISR, and DMASR. The 6-bit contents of one of the registers CSR, ISR, or DMASR define one out of 64 Memory seg- ments of 64 Kbytes within the 4 Mbytes address space. The register contents represent the 6 MSBs of the memory address, whereas the 16 LSBs of the address (intra-segment address) are given by the virtual 16-bit address (see Figure 28). 2.7 MMU REGISTERS The MMU uses 7 registers mapped into Group F, Page 21 of the Register File and 2 bits of the EMR2 register. Most of these registers do not have a default value after reset. 2.7.1 DPR[3:0]: Data Page Registers The DPR[3:0] registers allow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes. 2.7.1.1 Data Page Register Relocation If these registers are to be used frequently, they may be relocated in register group E, by program- ming bit 5 of the EMR2-R246 register in page 21. If this bit is set, the DPR[3:0] registers are located at R224-227 in place of the Port 0-3 Data Registers, which are re-mapped to the default DPR's loca- tions: R240-243 page 21. Data Page Register relocation is illustrated in Fig- ure 26. Figure 28. Addressing via CSR, ISR, and DMASR Fetching program Data Memory Fetching interrupt instruction accessed in DMA instruction or DMA access to Program Memory 16-bit virtual address 22-bit physical address 6 bits MMU registers CSR ISR DMASR 1 2 3 1 2 3 9 |
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