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59 / 429 page 59/429 ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) REGISTER DESCRIPTION (Cont’d) The meaning of the FESSx bit for sector x is given in Table 10. FLASH & E3 TM STATUS REGISTER 1 (FESR1) Address: 224003h /221003h-Read Only Reset value: 0000 0000 (00h) Bit 7 = ERER. Erase error (Read Only). This bit is set by hardware when an Erase error oc- curs during a Flash or an E3 TM write operation. This error is due to a real failure of a Flash cell, that can no longer be erased. This kind of error is fatal and the sector where it occurred must be dis- carded. This bit is automatically cleared when bit FEERR of the FESR0 register is cleared by soft- ware. 0: Erase OK 1: Erase error Bit 6 = PGER. Program error (Read Only). This bit is automatically set when a Program error occurs during a Flash or an E3 TM write operation. This error is due to a real failure of a Flash cell, that can no longer be programmed. The byte where this error occurred must be discarded (if it was in the E3 TM memory, the byte must be repro- grammed to FFh and then discarded, to avoid the error occurring again when that byte is internally moved). This bit is automatically cleared when bit FEERR of the FESR0 register is cleared by soft- ware. 0: Program OK 1: Flash or E3 TM Programming error Bit 5 = SWER. Swap or 1 over 0 Error (Read On- ly). This bit has two different meanings, depending on whether the current write operation is to Flash or E3 TM memory. In Flash memory this bit is automatically set when trying to program at 1 bits previously set at 0 (this does not happen when programming the Protec- tion bits). This error is not due to a failure of the Flash cell, but only flags that the desired data has not been written. In the E3 TM memory this bit is automatically set when a Program error occurs during the swapping of the unselected pages to the new sector when the old sector is full (see AN1152 for more details). This error is due to a real failure of a Flash cell, that can no longer be programmed. When this er- ror is detected, the embedded algorithm automati- cally exits the Page Update operation at the end of the Swap phase, without performing the Erase Phase 0 on the full sector. In this way the old data are kept, and through predefined routines in Test- Flash (Find Wrong Pages = 230029h and Find Wrong Bytes = 23002Ch), the user can compare the old and the new data to find where the error oc- curred. Once the error has been discovered the user must take to end the stopped Erase Phase 0 on the old sector (through another predefined routine in Test- Flash: Complete Swap = 23002Fh). The byte where the error occurred must be reprogrammed to FFh and then discarded, to avoid the error oc- curring again when that byte is internally moved. This bit is automatically cleared when bit FEERR of the FESR0 register is cleared by software. Bit 4:0 = Reserved. Table 10. Sector Status Bits FEERR FBUSY EBUSY FSUSP FESSx=1 meaning 1- - Write Error in Sector x 01 - Write operation on-going in sec- tor x 00 1 Sector Erase Suspended in sector x 0 0 0 Don’t care 76 543 21 0 ERER PGER SWER 9 |
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