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74ACQ574SJ bảng dữ liệu(PDF) 2 Page - Fairchild Semiconductor |
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74ACQ574SJ bảng dữ liệu(HTML) 2 Page - Fairchild Semiconductor |
2 / 11 page ©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ACQ574, 74ACTQ574 Rev. 1.3 2 Logic Symbols IEEE/IEC Functional Description The ACQ/ACTQ574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. Inputs Internal Outputs Function OE CP D Q ON HH LNCZ Hold HHH NC Z Hold HL LZ Load HH HZ Load LL LL Data Available LH HH Data Available LHL NC NC No Change in Data LH HNCNC No Change in Data |
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Mô tả tương tự - 74ACQ574SJ |
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