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FIN24ACMLX bảng dữ liệu(PDF) 6 Page - Fairchild Semiconductor |
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FIN24ACMLX bảng dữ liệu(HTML) 6 Page - Fairchild Semiconductor |
6 / 25 page © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN24AC Rev. 1.0.3 6 Serializer Operation Mode The serializer configurations are described in the following sections. The basic serialization circuitry works essentially the same in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the STROBE signal or not. When the CKREF equals STROBE, the CKREF and STROBE signals have an identical fre- quency of operation, but may or may not be phase aligned. When CKREF does not equal STROBE, each signal is dis- tinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal, provided that data can be ignored during the PLL lock phase. Once the PLL is stable and locked, the device can begin to capture and serialize data. Data is captured on the rising edge of the STROBE signal and serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. When in this mode, the internal dese- rializer circuitry is disabled; including the serial clock, serial data input buffers, the bi-directional parallel outputs, and the CKP word clock. The CKP word clock is driven HIGH. Figure 4. Serializer Timing Diagram (CKREF equals STROBE) If the same signal is not used for CKREF and STROBE, the CKREF signal must be run at a higher frequency than the STROBE rate to serialize the data correctly. The actual serial transfer rate remains at 26 times the CKREF frequency. A data bit value of zero is sent when no valid data is present in the serial bit stream. The operation of the serializer otherwise remains the same. The exact frequency that the reference clock needs is dependent upon the stabil- ity of the CKREF and STROBE signal. If the source of the CKREF signal imple- ments spread spectrum technology, the maximum frequency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-to- cycle variation, the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency. Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE) WORD n-1 WORD n-2 WORD n-1 WORD n DPI[1:24] CKREF DSO CKS0 b24 b25 b26 b1 b2 b3 b4 b1 b2 b3 b4 b5 b22 b23 b24 b25 b26 WORD n+1 WORD n WORD n-1 WORD n-1 WORD n No Data No Data CKREF DP[1:24] DSO CKS0 STROBE b1 b2 b3 b1 b2 b3 b4 b5 b6 b7 b22 b23 b24 b25 b26 WORD n+1 WORD n Serializer Operation: (Figure 4) MODE 1, 2, or 3 DIRI = 1, CKREF = STROBE Serializer Operation: (Figure 5), DIRI = 1, CKREF does not = STROBE |
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