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FIN24C bảng dữ liệu(PDF) 11 Page - Fairchild Semiconductor |
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FIN24C bảng dữ liệu(HTML) 11 Page - Fairchild Semiconductor |
11 / 25 page ©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN24C Rev. 1.0.2 11 Figure 10. Bi-Directional Differential I/O Circuitry PLL Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL generates internal timing signals capa- ble of transferring data at 26 times the incoming CKREF signal. The output of the PLL is a bit clock sent with the serial data stream. There are two ways to disable the PLL: by entering the Mode 0 state (S1 = S2 = 0) or upon detecting a LOW on both the S1 and S2 signals. Any of the other modes are entered by asserting either S1 or S2 HIGH and by pro- viding a CKREF signal. The PLL powers up and goes through a lock sequence. Wait the specified number of clock cycles prior to capturing valid data into the parallel port. When the µSerDes chipset transitions from a power-down state (S1, S2 = 0, 0) to a powered state (example S1, S2 = 1, 1), CKP on the deserializer transi- tions LOW for a short duration, then returns HIGH. Fol- lowing this, the signal level of the deserializer at CKP corresponds to the serializer signal levels. An alternate way of powering down the PLL is by stop- ping the CKREF signal either HIGH or LOW. Internal cir- cuitry detects the lack of transitions and shuts the PLL and serial I/O down. Internal references, however, are not disabled, allowing the PLL to power-up and re-lock in a lesser number of clock cycles than when exiting Mode 0. When a transition is seen on the CKREF signal, the PLL is reactivated. Application Mode Diagrams MODE = 3: Unidirectional Data Transfer Figure 11. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure 11 shows basic operation when a pair of SerDes is configured in an unidirectional operation mode. In Master Operation, the device: 1. Is configured as a serializer at power-up based on the value of the DIRI signal. 2. Accepts CKREF_M word clock and generate a bit clock with embedded word boundary. This bit clock is sent to the slave device through the CKSO port. 3. Receives parallel data on the rising edge of STROBE_M. 4. Generates and transmits serialized data on the DS signals source synchronous with CKSO. 5. Generates an embedded word clock for each strobe signal. In Slave Operation, the device: 1. Is configured as a deserializer at power-up based on the value of the DIRI signal. 2. Accepts an embedded word boundary bit clock on CKSI. 3. Deserializes the DS data stream using the CKSI input clock. 4. Writes parallel data onto the DP_S port and generates the CKP_S. CKP_S is only generated when a valid data word occurs. + – + – DS+ DS- Gated Termination (DS Pins Only) From Serializer To Deserializer From Control + – + – + – + – CKREF_M CKSO CKSI CKP_S DP[1:20, 23:24]_S Serializer Control BIT CK Gen. PLL Master Device Operating as a Serializer DIR = “1” S2 = S1 = “0” Slave Device Operating as a Deserializer DIR = “0” S2 = S1 = “0” Deserializer Control Work CK Gen Serializer Deserializer DS STROBE_M DP[1:22]_M |
Số phần tương tự - FIN24C |
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Mô tả tương tự - FIN24C |
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