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FIN12ACGFX bảng dữ liệu(PDF) 9 Page - Fairchild Semiconductor |
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FIN12ACGFX bảng dữ liệu(HTML) 9 Page - Fairchild Semiconductor |
9 / 24 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 9 Figure 9. Bi-Directional Differential I/O Circuitry Phase-Locked Loop (PLL) Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL generates internal timing signals capa- ble of transferring data at 14 times the incoming CKREF signal. The output of the PLL is a bit clock used to serial- ize the data. The bit clock is also sent source synchro- nously with the serial data stream. There are two ways to disable the PLL. The PLL can be disabled by entering the Mode 0 state (S1 = S2 = 0). The PLL disables immediately upon detecting a LOW on both the S1 and S2 signals. When any of the other modes are entered by asserting S1 or S2 HIGH and by providing a CKREF signal, the PLL powers up and goes through a lock sequence. Wait a specified number of clock cycles prior to capturing valid data into the parallel port and applying CKREF to STROBE. When the µSerDes chipset transitions from a power-down state (S1, S2 = 0.0) to a powered state (example S1, S2 = 1, 1), CKP on the deserializer transitions LOW for a short duration and returns HIGH. Following this, the signal level of the dese- rializer at CKP corresponds to the serializer signal levels. An alternate way of powering down the PLL is by stop- ping the CKREF signal either HIGH or LOW. Internal cir- cuitry detects the lack of transitions and shuts the PLL and serial I/O down. Internal references are not disabled, allowing for the PLL to power-up and re-lock in fewer clock cycles than when exiting Mode 0. When a transi- tion is seen on the CKREF signal, the PLL is reactivated. Application Mode Diagrams Modes 1, 2, 3: Unidirectional Data Transfer Figure 10. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure 10 shows basic operation when a pair of µSerDes is configured in an unidirectional operation mode. Master Operation: 1. During power-up, the device is configured as a serializer based on the value of the DIRI signal. 2. The device accepts CKREF_M word clock and gen- erates a bit clock with embedded word boundary. This bit clock is sent to the slave device through the CKSO port. 3. The device receives parallel data on the rising edge of STROBE_M. 4. The device generates and transmits serialized data on the DS signals, which is source synchronous with CKSO. 5. The device generates an embedded word clock for each strobe signal. Slave Operation: 1. The device is configured as a deserializer at power- up based on the value of the DIRI signal. 2. The device accepts an embedded word boundary bit clock on CKSI. 3. The device deserializes the DS data stream using the CKSI input clock. 4. The device writes parallel data onto the DP_S port and generates the CKP_S only when a valid data word occurs. + – + – DS+ DS- Gated Termination (DS Pins Only) From Serializer To Deserializer From Control + – + – + – + – CKREF_M CKSO CKSI CKP_S DP[1:12]_S Serializer Control BIT CK Gen. PLL Master Device Operating as a Serializer DIR = “1” Slave Device Operating as a Deserializer DIR = “0” Deserializer Control Work CK Gen Serializer Deserializer DS STROBE_M DP[1:12]_M |
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