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X1286V14Z bảng dữ liệu(PDF) 10 Page - Intersil Corporation |
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X1286V14Z bảng dữ liệu(HTML) 10 Page - Intersil Corporation |
10 / 25 page 10 FN8101.1 April 14, 2006 Each register is read and written through buffers. The non-volatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another sec- tion requires a new operation. Continued reads or writes, once reaching the end of a section, will wrap around to the start of the section. A read or write can begin at any address in the CCR. It is not necessary to set the RWEL bit prior to writing the status register. Section 5 supports a single byte read or write only. Continued reads or writes from this section terminates the operation. The state of the CCR can be read by performing a ran- dom read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next Register. ALARM REGISTERS There are two alarm registers whose contents mimic the contents of the RTC register, but add enable bits and exclude the 24 hour time selection bit. The enable bits specify which registers to use in the comparison between the Alarm and Real Time Registers. For example: – Setting the Enable Month bit (EMOn*) bit in combi- nation with other enable bits and a specific alarm time, the user can establish an alarm that triggers at the same time once a year. *n = 0 for Alarm 0: N = 1 for Alarm 1 Table 1. Clock/Control Memory Map Addr. Type Reg Name Bit Range 7 6 54 321 0 (optional) 003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF 01h 0037 RTC (SRAM) SSEC SS23 SS22 SS21 SS20 SS13 SS12 SS11 SS10 0-99 xxh 0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 xxh 0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 xxh 0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 xxh 0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 xxh 0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 xxh 0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 xxh 0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 xxh 0013 Control (EEPROM) DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h 0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h 0011 INT IM AL1E AL0E FO1 FO0 Read Only Read Only Read Only 00h 0010 BL BP2 BP1 BP0 WD1 WD0 Read Only Read Only Read Only 00h 000F Alarm1 (EEPROM) Y2K1 Read-only - Default = 20h 20 20h 000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h 000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion 000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h 000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h 000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h 0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h 0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h X1286 |
Số phần tương tự - X1286V14Z |
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Mô tả tương tự - X1286V14Z |
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