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ISL22349UFV14Z bảng dữ liệu(PDF) 11 Page - Intersil Corporation

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Giải thích chi tiết về linh kiện  Quad Digitally Controlled Potentiometers
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nhà sản xuất  INTERSIL [Intersil Corporation]
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11
FN6331.2
September 15, 2006
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22349 responds with an ACK. At this time, the device
enters its standby state (See Figure 14). Device can receive
more than one byte of data by auto incrementing the
address after each received byte. Note after reaching the
address 08h, the internal pointer “rolls over” to address 00h.
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write. Thus, non-volatile registers must be
written individually.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 15). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL22349 responds with an ACK. Then the ISL22349
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
ACK and a STOP condition) following the last bit of the last
Data Byte (See Figure 15).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 08h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
A
C
K
1
0
1
00
A
C
K
WRITE
SIGNAL AT SDA
00 0 0
A0
A1
A2
0
FIGURE 14. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
A
C
K
A
C
K
10
1
00
S
T
O
P
A
C
K
1
1
1
00
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
0
00 0
A0
A1
A2
A0
A1
A2
FIGURE 15. READ SEQUENCE
A
C
K
ISL22349


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