© 2001 Fairchild Semiconductor Corporation

DS011347

www.fairchildsemi.com

February 1992

Revised June 2001

74LVQ74

Low Voltage Dual D-Type

Positive Edge-Triggered Flip-Flop

General Description

The LVQ74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on the

positive edge of the clock pulse. Clock triggering occurs at

a voltage level of the clock pulse and is not directly related

to the transition time of the positive-going pulse. After the

Clock Pulse input threshold voltage has been passed, the

Data input is locked out and information present will not be

transferred to the outputs until the next rising edge of the

Clock Pulse input.

Asynchronous Inputs:

Clear and Set are independent of clock

Q and Q HIGH

Features

s Ideal for low power/low noise 3.3V applications

s Guaranteed simultaneous switching noise level and

dynamic threshold performance

s Guaranteed pin-to-pin skew AC performance

s Guaranteed incident wave switching into 75

Ω

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number

Package Number

Package Description

74LVQ74SC

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LVQ74SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Pin Names

Description

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs