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FIN1218 bảng dữ liệu(PDF) 7 Page - Fairchild Semiconductor

tên linh kiện FIN1218
Giải thích chi tiết về linh kiện  LVDS 21-Bit Serializers/De-Serializers
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Trang chủ  http://www.fairchildsemi.com
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FIN1218 bảng dữ liệu(HTML) 7 Page - Fairchild Semiconductor

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Transmitter AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and
Power-Down pin is above 1.5V.
Note 14: This output data pulse position works for both transmitter with 21 TTL inputs except the LVDS output bit mapping difference (see Figure 15). Figure
16 shows the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Note 15: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
tTCP
Transmit Clock Period
See Figure 6
11.76
T
50.0
ns
tTCH
Transmit Clock (TxCLKIn) HIGH Time
0.35
0.5
0.65
T
tTCL
Transmit Clock Low Time
0.35
0.5
0.65
T
tCLKT
TxCLKIn Transition Time (Rising and Failing)
(10% to 90%) See Figure 7
1.0
6.0
ns
tJIT
TxCLKIn Cycle-to-Cycle Jitter
3.0
ns
tXIT
TxIn Transition Time
1.5
6.0
ns
LVDS Transmitter Timing Characteristics
tTLH
Differential Output Rise Time (20% to 80%)
See Figure 4
0.75
1.5
ns
tTHL
Differential Output Fall Time (80% to 20%)
0.75
1.5
ns
tSTC
TxIn Setup to TxCLNIn
See Figure 6
2.5
ns
tHTC
TxIn Holds to TCLKIn
(f
85 MHz) (FIN1217 only)
0
ns
tTPDD
Transmitter Power-Down Delay
See Figure 13, (Note 13)
100
ns
tTCCD
Transmitter Clock Input to Clock Output Delay
See Figure 9
5.5
ns
Transmitter Clock Input to Clock Output Delay
(TA 25qC and with VCC 3.3V)
2.8
6.8
Transmitter Output Data Jitter (f
40 MHz) (Note 14)
tTPPB0
Transmitter Output Pulse Position of Bit 0
See Figure 16
0.25
0
0.25
ns
tTPPB1
Transmitter Output Pulse Position of Bit 1
a
0.25aa0.25
ns
tTPPB2
Transmitter Output Pulse Position of Bit 2
a
12a
0.25
2a
2a
0.25
ns
tTPPB3
Transmitter Output Pulse Position of Bit 3
f x 7
3a
0.25
3a
3a
0.25
ns
tTPPB4
Transmitter Output Pulse Position of Bit 4
4a
0.25
4a
4a
0.25
ns
tTPPB5
Transmitter Output Pulse Position of Bit 5
5a
0.25
5a
5a
0.25
ns
tTPPB6
Transmitter Output Pulse Position of Bit 6
6a
0.25
6a
6a
0.25
ns
Transmitter Output Data Jitter (f
65 MHz) (Note 14)
tTPPB0
Transmitter Output Pulse Position of Bit 0
See Figure 16
0.2
0
0.2
ns
tTPPB1
Transmitter Output Pulse Position of Bit 1
a
0.2
a
a
0.2
ns
tTPPB2
Transmitter Output Pulse Position of Bit 2
a
12a
0.2
2a
2a
0.2
ns
tTPPB3
Transmitter Output Pulse Position of Bit 3
f x 7
3a
0.2
3a
3a
0.2
ns
tTPPB4
Transmitter Output Pulse Position of Bit 4
4a
0.2
4a
4a
0.2
ns
tTPPB5
Transmitter Output Pulse Position of Bit 5
5a
0.2
5a
5a
0.2
ns
tTPPB6
Transmitter Output Pulse Position of Bit 6
6a
0.2
6a
6a
0.2
ns
Transmitter Output Data Jitter (f
85 MHz) (FIN1217 only) (Note 14)
tTPPB0
Transmitter Output Pulse Position of Bit 0
See Figure 16
0.2
0
0.2
ns
tTPPB1
Transmitter Output Pulse Position of Bit 1
a
0.2
a
a
0.2
ns
tTPPB2
Transmitter Output Pulse Position of Bit 2
a
12a
0.2
2a
2a
0.2
ns
tTPPB3
Transmitter Output Pulse Position of Bit 3
f x 7
3a
0.2
3a
3a
0.2
ns
tTPPB4
Transmitter Output Pulse Position of Bit 4
4a
0.2
4a
4a
0.2
ns
tTPPB5
Transmitter Output Pulse Position of Bit 5
5a
0.2
5a
5a
0.2
ns
tTPPB6
Transmitter Output Pulse Position of Bit 6
6a
0.2
6a
6a
0.2
ns
tJCC
FIN1217 Transmitter Clock Out Jitter
f
40 MHz
350
370
ps
(Cycle-to-Cycle)
f
65 MHz
210
230
See Figure 19
f
85 MHz (FIN1217 only)
110
150
tTPLLS
Transmitter Phase Lock Loop Set Time (Note 15)
See Figure 11, (Note 14)
10.0
ms


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