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9 / 14 page NBSG16VS http://onsemi.com 9 Table 10. AC CHARACTERISTICS for QFN−16 VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V Symbol Characteristic −40 °C 25 °C 85 °C Unit Min Typ Max Min Typ Max Min Typ Max fmax Maximum Frequency (See Figure 8) (Note 34) 10 (Note 37) 12 10 (Note 37) 12 10 (Note 37) 12 GHz tPLH, tPHL Propagation Delay to Output Differential (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q 100 100 140 135 180 180 100 100 140 135 180 180 100 80 140 135 180 220 ps tSKEW Duty Cycle Skew (Note 35) 3 20 3 15 3 10 ps tJITTER RMS Random Clock Jitter fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s 0.5 TBD 2 0.5 TBD 2 0.5 TBD 2 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 36) 75 2600 75 2600 75 2600 mV tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q 30 30 45 40 55 50 30 30 45 40 55 50 30 30 45 40 55 50 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 34. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. Input edge rates 40 ps (20% − 80%). 35. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 36. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV). 37. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 8). Table 11. AC CHARACTERISTICS for QFN−16 VCC = 0 V; −3.0 V tVEE v −2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V Symbol Characteristic −40 °C 25 °C 85 °C Unit Min Typ Max Min Typ Max Min Typ Max fmax Maximum Frequency (See Figure 9) (Note 38) 10 (Note 41) 12 10 (Note 41) 12 10 (Note 41) 12 GHz tPLH, tPHL Propagation Delay to Output Differential (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q 100 100 140 135 180 180 100 100 140 135 180 180 80 100 140 135 180 220 ps tSKEW Duty Cycle Skew (Note 39) 3 20 3 15 3 10 ps tJITTER RMS Random Clock Jitter fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s 0.5 TBD 3 0.5 TBD 3 0.5 TBD 3 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 40) 75 2600 75 2600 75 2600 mV tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q 25 22 50 45 70 60 25 22 50 45 70 60 25 22 50 45 70 60 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 38. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. Input edge rates 40 ps (20% − 80%). 39. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 40. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV). 41. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 9). |
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