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NBSG11BAEVB bảng dữ liệu(PDF) 2 Page - ON Semiconductor

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Giải thích chi tiết về linh kiện  2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL Outputs
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Figure 1. BGA−16 Pinout (Top View)
VTCLK
CLK
CLK
VEE
VTCLK
NC
VEE
NC
NC
Q1
VCC
VCC
NC
Q0
Q0
Q1
A
B
C
D
12
3
4
VEE
NC
NC
VCC
VEE
NC
NC
VCC
Q0
Q0
Q1
Q1
VTCLK
CLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG11
Exposed Pad (EP)
Figure 2. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
BGA
QFN
D1
1
VTCLK
Internal 50
W Termination Pin. See Table 2.
C1
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 k
W to VEE and 36.5 kW to VCC.
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 k
W to VEE.
A1
4
VTCLK
Internal 50
W Termination Pin. See Table 2.
B2,C2
5,16
VEE
Negative Supply Voltage
A2,A3,D2,
D3
6,7,14,15
NC
No Connect
B3,C3
8,13
VCC
Positive Supply Voltage
A4
9
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50
W to
VTT = VCC − 2.0 V.
B4
10
Q1
RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50
W to
VTT = VCC − 2.0 V.
C4
11
Q0
RSECL Output
Inverted Differential output 0. Typically Terminated with 50
W to
VTT = VCC − 2.0 V.
D4
12
Q0
RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50
W to
VTT = VCC − 2 V.
N/A
EP
Exposed Pad (Note 2)
1. The NC pins are electrically connected to the die and must be left open.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat−sinking conduit.
3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and
if no signal is applied then the device will be susceptible to self−oscillation.


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   2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL* Outputs
April, 2003 - Rev. 6
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