MC33362

http://onsemi.com

9

OPERATING DESCRIPTION

Introduction

The MC33362 represents a new higher level of integration

by providing all the active high voltage power, control, and

protection circuitry required for implementation of a

flyback or forward converter on a single monolithic chip.

This device is designed for direct operation from a rectified

120 VAC line source and requires a minimum number of

external components to implement a complete converter. A

description of each of the functional blocks is given below,

and the representative block and timing diagrams are shown

in Figures 19 and 20.

Oscillator and Current Mirror

The oscillator frequency is controlled by the values

programs the oscillator charge/discharge current via the

and discharged by an equal magnitude internal current

source and sink. This generates a symmetrical 50 percent

duty cycle waveform at Pin 7, with a peak and valley

threshold of 2.6 V and 0.6 V respectively. During the

pulse that holds the inverting input of the AND gate Driver

high. This causes the Power Switch gate drive to be held in

a low state, thus producing a well controlled amount of

output deadtime. The amount of deadtime is relatively

constant with respect to the oscillator frequency when

operating below 1.0 MHz. The maximum Power Switch

duty cycle at Pin 16 can be modified from the internal 50%

limit by providing an additional charge or discharge current

Pin 7 to ground. To decrease the maximum duty cycle, a

Regulator Output. Figure 5 shows an obtainable range of

Figure 21. Maximum Duty Cycle Modification

PWM

Current

Regulator Output

1.0

R

C

8

6

2.25 I

I

T

T

Mirror

4 I

Oscillator

Comparator

RD

RC

7

Current

Limit

Reference

Blanking

Pulse

The formula for the charge/discharge current along with

the oscillator frequency are given below. The frequency

Limit Comparator threshold.

Ichg dscg +

5.4

RT

f [

Ichg dscg

4CT

PWM Comparator and Latch

The pulse width modulator consists of a comparator with

the oscillator ramp voltage applied to the non−inverting

input, while the error amplifier output is applied into the

inverting input. The Oscillator applies a set pulse to the

valley voltage, Power Switch conduction is initiated. When

output, the PWM Latch is reset, thus terminating Power

Switch conduction for the duration of the oscillator ramp−up

period. This PWM Comparator/Latch

combination

prevents multiple output pulses during a given oscillator

clock cycle. The timing diagram shown in Figure 20

illustrates the Power Switch duty cycle behavior versus the

Compensation voltage.

Current Limit Comparator and Power Switch

The MC33362 uses cycle−by−cycle current limiting as a

means of protecting the output switch transistor from

overstress. Each on−cycle is treated as a separate situation.

Current limiting is implemented by monitoring the output

switch current buildup during conduction, and upon sensing

an overcurrent condition, immediately turning off the switch

for the duration of the oscillator ramp−up period.

The Power Switch is constructed as a SENSEFET

allowing a virtually lossless method of monitoring the drain

current. It consists of a total of 3770 cells, of which 50 are

connected to a 9.0

W ground−referenced sense resistor. The

Current Sense Comparator detects if the voltage across the

sense resistor exceeds the reference level that is present at

the inverting input. If exceeded, the comparator quickly

resets the PWM Latch, thus protecting the Power Switch.

The current limit reference level is generated by the 2.25 I

output of the Current Mirror. This current causes a reference

voltage to appear across the 450

W resistor. This voltage

level, as well as the Oscillator charge/discharge current are

desired Oscillator frequency. A graph of the Power Switch

related formula below.

Ipk + 12.3

RT

1000

− 1.115