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MC14512B bảng dữ liệu(PDF) 5 Page - ON Semiconductor |
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5 / 7 page MC14512B http://onsemi.com 5 LOGIC DIAGRAM 13 12 11 1 2 3 4 5 6 7 9 X7 X6 X5 X4 X3 X2 X1 X0 B C A 15 10 14 DISABLE INHIBIT VDD Z VSS 1 1 IN OUT IN 2 OUT 2 TRANSMISSION GATE SELECTED DEVICE MC14512B MC14512B MC14512B IOD ITL ITL IL LOAD DATA BUS 3−STATE MODE OF OPERATION Output terminals of several MC14512B 8−Bit Data Selectors can be connected to a single date bus as shown. One MC14512B is selected by the 3−state control, and the remaining devices are disabled into a high−impedance “off” state. The number of 8−bit data selectors, N, that may be connected to a bus line is determined from the output drive current, IOD, 3−state or disable output leakage current, ITL, and the load current, IL, required to drive the bus line (including fanout to other device inputs), and can be calculated by: ITL N = + 1 IOD – IL N must be calculated for both high and low logic state of the bus line. |
Số phần tương tự - MC14512B |
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Mô tả tương tự - MC14512B |
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