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MC14174BCP bảng dữ liệu(PDF) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MC14174B/D
MC14174B
Hex Type D Flip−Flop
The MC14174B hex type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flip−flops share common clock and reset inputs.
The reset is active low, and independent of the clock.
Features
Static Operation
All Inputs and Outputs Buffered
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Functional Equivalent to TTL 74174
Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
VDD
− 0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout
− 0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
±10
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
− 55 to +125
°C
Storage Temperature Range
− 65 to +150
°C
Lead Temperature (8−Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Device
Package
Shipping
ORDERING INFORMATION
MC14174BCP
PDIP−16
25 Units/Rail
MC14174BD
SOIC−16
48 Units/Rail
MC14174BDR2
SOIC−16
2500/Tape & Reel
http://onsemi.com
MC14174BDR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
MC14174BDG
SOIC−16
(Pb−Free)
48 Units/Rail
MC14174BCPG
PDIP−16
(Pb−Free)
25 Units/Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
A
= Assembly Location
WL
= Wafer Lot
YY, Y = Year
WW
= Work Week
G
= Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
1
16
14174BG
AWLYWW
16
1
MC14174BCP
AWLYYWWG
1
1


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