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MC12026A bảng dữ liệu(PDF) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 8
1
Publication Order Number:
MC12026A/D
MC12026A
1.1 GHz Dual Modulus
Prescaler
Description
The MC12026 is a high frequency, low voltage dual modulus
prescaler used in phase−locked loop (PLL) applications.
The MC12026A can be used with CMOS synthesizers requiring
positive edges to trigger internal counters in a PLL to provide tuning
signals up to 1.1 GHz in programmable frequency steps.
A Divide Ratio Control (SW) permits selection of an 8/9 or 16/17
divide ratio as desired.
The Modulus Control (MC) selects the proper divide number after
SW has been biased to select the desired divide ratio.
Features
1.1 GHz Toggle Frequency
Supply Voltage 4.5 to 5.5 V
Low Power 4.0 mA Typical
Operating Temperature Range of −40 to 85°C
The MC12026 is Pin Compatible with the MC12022
Short Setup Time (tset ) 6.0 ns Typical @ 1.1 GHz
Modulus Control Input Level is Compatible with Standard CMOS
and TTL
Pb−Free Packages are Available
Table 1. FUNCTIONAL TABLE
SW
MC
Divide Ratio
H
H
8
H
L
9
L
H
16
L
L
17
1. SW: H = VCC, L = Open. A logic L can also be applied by grounding this pin,
but this is not recommended due to increased power consumption.
2. MC: H = 2.0 V to VCC, L = GND to 0.8 V.
Table 2. MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
Power Supply Voltage, Pin 2
VCC
−0.5 to 7.0
Vdc
Operating Temperature Range
TA
−40 to 85
°C
Storage Temperature Range
Tstg
−65 to 150
°C
Modulus Control Input, Pin 6
MC
−0.5 to 6.5
Vdc
Maximum Output Current, Pin 4
IO
10.0
mA
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
NOTE: ESD data available upon request.
http://onsemi.com
PIN CONNECTIONS
(Top View)
IN
8
IN
VCC
SW
OUT
NC
MC
GND
7
6
5
1
2
3
4
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAM
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
1
8
026A
ALYW
G
1
8
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION


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