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MC3423 bảng dữ liệu(PDF) 5 Page - ON Semiconductor |
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MC3423 bảng dữ liệu(HTML) 5 Page - ON Semiconductor |
5 / 10 page MC3423 http://onsemi.com 5 Power Supply #1 R1 Power Supply #2 + − + − 10k Q1 1.0k 5 7 1 7 6 1 Figure 8. Circuit Configuration for Activating One MC3423 from Another Note that both supplies have their negative output leads tied together (i.e., both are positive supplies). If their positive leads are common (two negative supplies) the emitter of Q1 would be moved to the positive lead of supply 1 and R1 would therefore have to be resized to deliver the appropriate drive to Q1. Crowbar SCR Considerations Referring to Figure 11, it can be seen that the crowbar SCR, when activated, is subject to a large current surge from the output capacitance, Cout. This capacitance consists of the power supply output caps, the load’s decoupling caps, and in the case of Figure 11A, the supply’s input filter caps. This surge current is illustrated in Figure 12, and can cause SCR failure or degradation by any one of three mechanisms: di/dt, absolute peak surge, or I2t. The interrelationship of these failure methods and the breadth of the applications make specification of the SCR by the semiconductor manufacturer difficult and expensive. Therefore, the designer must empirically determine the SCR and circuit elements which result in reliable and effective OVP operation. However, an understanding of the factors which influence the SCR’s di/dt and surge capabilities simplifies this task. di/dt As the gate region of the SCR is driven on, its area of conduction takes a finite amount of time to grow, starting as a very small region and gradually spreading. Since the anode current flows through this turned−on gate region, very high current densities can occur in the gate region if high anode currents appear quickly (di/dt). This can result in immediate destruction of the SCR or gradual degradation of its forward blocking voltage capabilities − depending on the severity of the occasion. VT, TRIP VOLTAGE (V) 0 5.0 10 15 20 25 30 Min 30 20 10 0 Typ R2 = 2.7 k Max Figure 9. R1 versus Trip Voltage 35 30 25 20 15 10 0 1020 30 4050 60 70 80 RG, GATE CURRENT LIMITING RESISTOR ( W) RG(min) = 0 if VCC < 11 V Figure 10. Minimum RG versus Supply Voltage td, DELAY TIME (ms) 12 3 5 7 1 1 5 2 1 0.0001 0.001 0.01 0.1 1.0 0.001 0.01 0.1 1.0 10 Figure 11. Capacitance versus Minimum Overvoltage Duration |
Số phần tương tự - MC3423_05 |
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Mô tả tương tự - MC3423_05 |
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