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2 / 9 page MC100LVEP14 http://onsemi.com 2 Figure 1. 20−Lead Pinout (Top View) and Logic Diagram Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Q2 Q1 Q3 Q1 17 18 16 15 14 13 12 4 3 5678 9 11 10 CLK1 CLK0 CLK0 Q0 19 20 2 1 EN Q2 Q0 Q3 Q4 Q4 CLK1 10 D Q VCC VCC VBB VEE CLK_SEL Table 1. PIN DESCRIPTION Pin Function CLK0*, CLK0** ECL/PECL/HSTL CLK Input CLK1*, CLK1** ECL/PECL/HSTL CLK Input Q0:4, Q0:4 ECL/PECL Outputs CLK_SEL* ECL/PECL Active Clock Select Input EN* ECL Sync Enable VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply * Pins will default low when left open. **Pins will default to VCC/2 when left open. Table 2. FUNCTION TABLE CLK0 CLK1 CLK_SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* *On next negative transition of CLK0 or CLK1 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg TSSOP−20 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 357 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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