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MC100LVELT20DR2G bảng dữ liệu(PDF) 2 Page - ON Semiconductor

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Giải thích chi tiết về linh kiện  3.3VLVTTL/LVCMOS to Differential LVPECL Translator
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MC100LVELT20
http://onsemi.com
2
1
2
3
45
6
7
8
D
GND
VCC
Q
NC
Q
NC
NC
LVTTL
LVPECL
Figure 1. 8−Lead Pinout and Logic Diagram
(Top View)
Table 1. PIN DESCRIPTION
Pin
Function
Q, Q
Differential PECL Outputs
D
LVTTL Input
VCC
Positive Supply
GND
Ground
NC
No Connect
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
150 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Power Supply
GND = 0 V
6
V
VI
Input Voltage
GND = 0 V
VI  VCC
6
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
Tsol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.


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MC100LVELT20DR2G ONSEMI-MC100LVELT20DR2G Datasheet
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   3.3V LVTTL/LVCMOS to Differential LVPECL Translator
July, 2016 ??Rev. 1
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