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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 6
1
Publication Order Number:
MC100EL91/D
MC100EL91
5 V Triple PECL Input to
−5 V ECL Output Translator
Description
The MC100EL91 is a triple PECL input to ECL output translator.
The device receives standard voltage differential PECL signals,
determined by the VCC supply level, and translates them to differential
−5 V ECL output signals. (For translation of LVPECL to −3.3 V ECL
output, see MC100LVEL91.)
To accomplish the level translation, the EL91 requires three power
rails. The VCC supply should be connected to the positive supply, and
the VEE pin should be connected to the negative power supply. The
GND pins are connected to the system ground plane. Both VEE and
VCC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at VCC/2
and the D input will be pulled to GND. This condition will force the Q
output to a low, ensuring stability.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
670 ps Typical Propagation Delay
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation
Operating Range:VCC = 4.75 V to 5.5 V;
VEE = −4.2 V to −5.5 V; GND = 0 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at GND
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 282 devices
Pb−Free Package is Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAM*
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G= Pb−Free Package
SO−20 WB
DW SUFFIX
CASE 751D
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
20
1
100EL91
AWLYYWWG


Số phần tương tự - MC100EL91DWG

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