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MC74VHC74 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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1 / 6 page © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 5 1 Publication Order Number: MC74VHC74/D MC74VHC74 Dual D−Type Flip−Flop with Set and Reset The MC74VHC74 is an advanced high speed CMOS D−type flip−flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • High Speed: fmax = 170MHz (Typ) at VCC = 5V • Low Power Dissipation: ICC = 2mA (Max) at TA = 25°C • High Noise Immunity: VNIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs • Balanced Propagation Delays • Designed for 2.0 V to 5.5 V Operating Range • Low Noise: VOLP = 0.8 V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300 mA • ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V • Chip Complexity: 128 FETs or 32 Equivalent Gates • Pb−Free Packages are Available* Figure 1. LOGIC DIAGRAM RD1 D1 CP1 SD1 RD2 D2 CP2 SD2 1 2 3 4 13 12 11 10 5 6 9 8 Q1 Q1 Q2 Q2 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAMS TSSOP−14 DT SUFFIX CASE 948G 1 SOEIAJ−14 M SUFFIX CASE 965 SOIC−14 D SUFFIX CASE 751A 1 1 See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ORDERING INFORMATION http://onsemi.com A = Assembly Location WL, L = Wafer Lot Y, YY = Year WW, W = Work Week G or G = Pb−Free Package 1 14 VHC74 ALYWG VHC74G AWLYWW 1 14 VHC 74 ALYWG G 1 14 (Note: Microdot may be in either location) FUNCTION TABLE Inputs Outputs SD RD CP D Q Q LH X X HL HL X X LH L L X X H* H* HH H H L HH L L H H H L X No Change H H H X No Change H H X No Change *Both outputs will remain high as long as Set and Re- set are low, but the output states are unpredictable if Set and Reset go high simultaneously. |
Số phần tương tự - MC74VHC74 |
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Mô tả tương tự - MC74VHC74 |
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