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Giải thích chi tiết về linh kiện  Quad 2-Input NAND Gate With 5 V?뭈olerant Inputs
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
TA = −40 to 85°C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
tPLH,
tPHL
Propagation Delay, Input to
Output
VCC = 2.7V
CL = 15 pF
CL = 50 pF
6.3
8.8
11.4
14.9
1.0
1.0
13.5
17.0
ns
VCC = 3.3 ± 0.3V
CL = 15 pF
CL = 50 pF
4.8
7.3
7.1
10.6
1.0
1.0
8.5
12.0
tOSHL
tOSLH
Output−to−Output Skew
(Note 1)
VCC = 2.7 V
CL = 50 pF
VCC = 3.3 ±0.3 V
CL = 50 pF
1.5
1.5
1.5
1.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
TA = 25°C
TA = −40 to 85°C
Symbol
Parameter
Min
Typ
Max
Min
Max
Unit
Cin
Input Capacitance
4
10
10
pF
CPD
Power Dissipation Capacitance (Note 2)
18
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 4 (per gate). CPD is used to determine the
no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 3.3 V, Measured in SOIC Package)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.5
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.3
−0.5
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
Figure 3. Switching Waveforms
VCC
GND
50%
50% VCC
A or B
O
tPHL
tPLH
*Includes all probe and jig capacitance
Figure 4. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT


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