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MC100H641FN bảng dữ liệu(PDF) 7 Page - ON Semiconductor |
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7 / 10 page MC10H641, MC100H641 http://onsemi.com 7 Rise/Fall Skew Determination The rise−to−fall skew is defined as simply the difference between the TPLH and the TPHL propagation delays. This skew for the H641 is dependent on the VCC applied to the device. Notice from Figure 4 the opposite relationship of TPD versus VCC between TPLH and TPHL. Because of this the rise−to−fall skew will vary depending on VCC. Since in all likelihood it will be impossible to establish the exact value for VCC, the expected variation range for VCC should be used. If this variation will be the ± 5% shown in the data sheet the rise−to−fall skew could be established by simply subtracting the fastest TPLH from the slowest TPHL; this exercise yields 1.41 ns. If a tighter VCC range can be realized Figure 4 can be used to establish the rise−to−fall skew. Specification Limit Determination Example The situation pictured in Figure 6 will be analyzed as an example. The central clock is distributed to two different cards; on one card a single H641 is used to distribute the clock while on the second card two H641’s are required to supply the needed clocks. The data sheet as well as the graphical information of this section will be used to calculate the skew between H641a and H641b as well as the skew between all three of the devices. Only the TPLH will be analyzed, the TPHL numbers can be found using the same technique. The following assumptions will be used: − All outputs will be loaded with 50 pF − All outputs will toggle at 30 MHz − The VCC variation between the two boards is ± 3 % − The temperature variation between the three devices is ± 15°C around an ambient of 45°C. − 500 lfpm air flow The first task is to calculate the junction temperature for the devices under these conditions. Using the power equation yields: PD =ICC (no load) * VCC + VCC * VS * f * CL * # outputs =4.3 * 48m A * 5.0 V + 5.0 V * 3.0 V * 30 MHz * 50 pF * 9 =432 mW + 203 mW = 635 mW Using the thermal resistance graph of Figure 2 yields a thermal resistance of 41°C/W which yields a junction temperature of 71°C with a range of 56°C to 86°C. Using the TPD versus Temperature curve of Figure 3 yields a propagation delay of 5.42 ns and a variation of 0.19 ns. Since the design will not experience the full ± 5% VCC variation of the data sheet the 1.0 ns window provided will be unnecessarily conservative. Using the curve of Figure 4 shows a delay variation due to a ± 3% VCC variation of ± 0.075 ns. Therefore the 1.0 ns window can be reduced to 1.0 ns − (0.27 ns − 0.15 ns) = 0.88 ns. Since H641a and H641b are on the same board we will assume that they will always be at the same VCC; therefore the propagation delay window will only be 1 ns − 0.27 ns = 0.73 ns. Putting all of this information together leads to a skew between all devices of 0.19 ns + 0.88 ns (temperature + supply, and inherent device), while the skew between devices A and B will be only 0.19 ns + 0.73 ns (temperature + inherent device only). In both cases, the propagation delays will be centered around 5.42 ns, resulting in the following tPLH windows: TPLH = 4.92 ns − 5.99 ns; 1.07 ns window (all devices) TPLH= 5.00 ns − 5.92 ns; 0.92 ns window (devices a & b) Of course the output−to−output skew will be as shown in the data sheet since all outputs are equally loaded. This process may seem cumbersome, however the delay windows, and thus skew, obtained are significantly better than the conservative worst case limits provided at the beginning of this note. For very high performance designs, this extra information and effort can mean the difference between going ahead with prototypes or spending valuable engineering time searching for alternative approaches. Q0 Q8 TTL ECL H641a Q0 Q8 TTL ECL H641b Q0 Q8 TTL ECL H641c Card 1 Card 2 Figure 6. Example Application |
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Mô tả tương tự - MC100H641FN |
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