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MC10H135FNR2 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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1 / 7 page © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 8 1 Publication Order Number: MC10H135/D MC10H135 Dual J−K Master−Slave Flip−Flop Description The MC10H135 is a dual J−K master−slave flip−flop. The device is provided with an asynchronous set(s) and reset(R). These set and reset inputs overide the clock. A common clock is provided with separate J−K inputs. When the clock is static, the JK inputs do not effect the output. The output states of the flip flop change on the positive transition of the clock. Features • Propagation delay, 1.5 ns Typical • Power Dissipation, 280 mW Typical/Pkg. (No Load) • ftog 250 MHz Max • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K™ Compatible • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. CDIP−16 L SUFFIX CASE 620A MARKING DIAGRAMS* PDIP−16 P SUFFIX CASE 648 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION SOEIAJ−16 CASE 966 16 1 16 1 MC10H135P AWLYYWWG 1 16 MC10H135L AWLYYWW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G= Pb−Free Package 10H135 ALYWG PLLC−20 FN SUFFIX CASE 775 20 1 10H135G AWLYYWW 120 |
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