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MC10H210PG bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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1 / 6 page © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 7 1 Publication Order Number: MC10H210/D MC10H210 Dual 3−Input 3−Output OR Gate Description The MC10H210 is designed to drive up to six transmission lines simultaneously. The multiple outputs of this device also allow the wire ORing of several levels of gating for minimization of gate and package count. The ability to control three parallel lines with minimum propagation delay from a single point makes the MC10H210 particularly useful in clock distribution applications where minimum clock skew is desired. Features • Propagation Delay Average, 1.0 ns Typical • Power Dissipation, 160 mW Typical • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K™ Compatible • Pb−Free Packages are Available* LOGIC DIAGRAM DIP PIN ASSIGNMENT VCC1 AOUT AOUT AOUT AIN AIN AIN VEE VCC2 VCC1 BOUT BOUT BOUT BIN BIN BIN 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 12 11 10 9 13 14 2 7 6 5 3 4 VCC1 = PINS 1, 15 VCC2 = PIN 16 VEE = PIN 8 Pin assignment is for Dual−in−Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. CDIP−16 L SUFFIX CASE 620A MARKING DIAGRAMS* PDIP−16 P SUFFIX CASE 648 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ORDERING INFORMATION SOEIAJ−16 CASE 966 16 1 16 1 MC10H210P AWLYYWWG 1 16 MC10H210L AWLYYWW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G= Pb−Free Package 10H210 ALYWG PLLC−20 FN SUFFIX CASE 775 20 1 10H210G AWLYYWW 120 |
Số phần tương tự - MC10H210PG |
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Mô tả tương tự - MC10H210PG |
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