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MC100EP139DWG bảng dữ liệu(PDF) 8 Page - ON Semiconductor

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Giải thích chi tiết về linh kiện  3.3V / 5V ECL 첨2/4, 첨4/5/6 Clock Generation Chip
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MC10EP139, MC100EP139
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Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
−40°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fmax
Maximum Frequency
(See Figure 5 Fmax/JITTER)
> 1
> 1
> 1
GHz
tPLH,
tPHL
Propagation Delay
CLK, Q (Diff)
MR, Q
550
700
700
800
800
900
600
700
750
850
900
1000
675
800
825
950
975
1100
ps
tRR
Reset Recovery
200
100
200
100
200
100
ps
ts
Setup Time
EN, CLK
DIVSEL, CLK
200
400
120
180
200
400
120
180
200
400
120
180
ps
th
Hold Time
CLK, EN
CLK, DIVSEL
100
200
50
140
100
200
50
140
100
200
50
140
ps
tPW
Minimum Pulse Width
MR
550
450
550
450
550
450
ps
tSKEW
Within Device Skew
Q, Q
Device−to−Device Skew (Note 21)
50
200
100
300
50
200
100
300
50
200
100
300
ps
tJITTER
Random Clock Jitter (RMS)
(See Figure 5 Fmax/JITTER)
0.2
< 1.0
0.2
< 1.0
0.2
< 1.5
ps
VPP
Input Voltage Swing (Differential Con-
figuration)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% − 80%)
110
180
250
125
190
275
150
215
300
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
21.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.


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