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© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 6
1
Publication Order Number:
MC10EP52/D
MC10EP52, MC100EP52
3.3V / 5VECL Differential
Data and Clock D Flip−Flop
Description
The MC10EP/100EP52 is a differential data, differential clock D
flip−flop. The device is pin and functionally equivalent to the EL52
device.
Data enters the master portion of the flip−flop when the clock is
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
The EP52 employs input clamping circuitry so that under open input
conditions (pulled down to VEE) the outputs of the device will remain
stable.
The 100 Series contains temperature compensation.
Features
330 ps Typical Propagation Delay
Maximum Frequency u 4 GHz Typical
PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode: VCC = 0 V with VEE = −3.0 V to −5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at VEE
Pb−Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
H
= MC10
A = Assembly Location
K
= MC100 L
= Wafer Lot
5T
= MC10
Y = Year
3O = MC100 W = Work Week
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ALYWG
G
HP52
ALYWG
G
KP52
MARKING
DIAGRAMS*
SOIC−8
D SUFFIX
CASE 751
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
1
8
http://onsemi.com
1
8
HEP52
ALYW
G
1
8
KEP52
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
14
14
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION


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