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MC100EP56DTR2 bảng dữ liệu(PDF) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 14
1
Publication Order Number:
MC10EP56/D
MC10EP56, MC100EP56
3.3V / 5VECL Dual
Differential 2:1 Multiplexer
Description
The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or other skew sensitive signals. Multiple VBB pins are
provided.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The device features both individual and common select inputs to
address both data path and random logic applications.
The 100 Series contains temperature compensation.
Features
360 ps Typical Propagation Delays
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
Open Input Default State
Safety Clamp on Inputs
Separate and Common Select
Q Output Will Default LOW with Inputs Open or at VEE
VBB Outputs
Pb−Free Packages are Available
xxxx
= MC10 or 100
D
= Date Code
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G, G
= Pb−Free Package
SOIC−20
DW SUFFIX
CASE 751D
MARKING DIAGRAMS*
TSSOP−20
DT SUFFIX
CASE 948R
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
20
1
MC100EP56
AWLYYWWG
XXXX
EP56
ALYWG
G
1
20
QFN−20
MN SUFFIX
CASE 485E
XXXX
EP56
ALYWG
G


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