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1 / 11 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 9 1 Publication Order Number: MC10EP31/D MC10EP31, MC100EP31 3.3V / 5VECL D Flip−Flop with Set and Reset Description The MC10/100EP31 is a D flip−flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip−flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. Features The 100 Series contains temperature compensation. • 340 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V • Open Input Default State • Q Output Will Default LOW with Inputs Open or at VEE • Pb−Free Packages are Available A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package H = MC10 K = MC100 5O = MC10 3J = MC100 M = Date Code SOIC−8 D SUFFIX CASE 751 MARKING DIAGRAMS* TSSOP−8 DT SUFFIX CASE 948R ALYWG G HP31 ALYWG G KP31 1 8 1 8 1 8 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ORDERING INFORMATION 1 8 HEP31 ALYW G 1 8 KEP31 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 14 (Note: Microdot may be in either location) |
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