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MC100E196FNR2 bảng dữ liệu(PDF) 8 Page - ON Semiconductor

tên linh kiện MC100E196FNR2
Giải thích chi tiết về linh kiện  5V ECL Programmable Delay Chip
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MC10E196, MC100E196
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When the SET MAX pin of chip #1 is asserted the D0 and
D1 latches will be reset while the rest of the latches will be
set. In addition, to maintain monotonicity an additional gate
delay is selected in the cascade circuitry. As a result when D7
of chip #1 is asserted the delay increases from 31.75 gates
to 32 gates. A 32 gate delay is the maximum delay setting for
the E196.
When cascading multiple PDC’s it will prove more cost
effective to use a single E196 for the Most Significant Bit
(MSB) of the chain while using E195 for the lower order
bits. This is due to the fact that only one fine tune input is
needed to further reduce the delay step resolution.
ADDRESS BUS (A0−A6)
A7
INPUT
D1
D0
LEN
VEE
IN
IN
VBB
VCC
VCC0
Q
Q
VCC0
D1
D0
LEN
VEE
IN
IN
VBB
VCC
VCC0
Q
Q
VCC0
OUTPUT
E196
Chip #1
E196
Chip #2
Figure 3. Cascading Interconnect Architecture
FTUNE
LINEAR
INPUT
FTUNE
SET MIN
SET MAX
TO SELECT MULTIPLEXERS
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
D0
Q0
LEN
Reset Reset
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LEN
LEN
LEN
LEN
LEN
LEN
LEN
CASCADE
CASCADE
Figure 4. Expansion of the Latch Section of the E196 Block Diagram
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset


Số phần tương tự - MC100E196FNR2

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
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ON Semiconductor
MC100E196 ONSEMI-MC100E196 Datasheet
148Kb / 7P
   PROGRAMMABLE DELAY CHIP
1996 REV 2
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Mô tả tương tự - MC100E196FNR2

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