MC33067PG datasheet(9/16 Pages) ONSEMI

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MC34067, MC33067

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9

The minimum frequency is programmed by ROSC using

Equation 1:

COSC

where tPD is the internal propagation delay.

(eq. 1)

R

1

ƒ

tPD

n

C

t

70 ns

0.348

−

=

−

OSC

(min)

(max)

OSC

5.1

3.6

The maximum oscillator frequency is set by the current

through resistor RVFO. The current required to discharge

COSC at the maximum oscillator frequency can be calculated

by Equation 2:

COSC

1.5C

(eq. 2)

OSC

I

1

ƒ

5.1 − 3.6

=

(max)

ƒ(max)

The discharge current through ROSC must also be known

and can be calculated by Equation 3:

ƒ(min)

COSC

ROSC

1.5

ε

I

1

ƒ

5.1 − 3.6

=

(min)

R

ROSC

COSC

ROSC

=

ROSC

ε

1

−

OSC

(eq. 3)

Resistor RVFO can now be calculated by Equation 4:

R=

VFO

I(max)

IR

−

2.5 − VEAsat

OSC

(eq. 4)

One−Shot Timer

The One−Shot is designed to disable both outputs

simultaneously providing a deadtime before either output is

enabled. The One−Shot capacitor (CT) is charged

concurrently with the oscillator capacitor by transistor Q1,

as shown in Figure 16. The one−shot period begins when the

oscillator comparator turns off Q1, allowing CT to

discharge. The period ends when resistor RT discharges CT

to the threshold of the One−Shot comparator. The lower

threshold of the One−Shot is 3.6 V. By choosing CT, RT can

by solved by Equation 5:

5.1

3.6

CT

R

t OS

C

0.348

=

T

t OS

n

(eq. 5)

Errors in the threshold voltage and propagation delays

through the output drivers will affect the One−Shot period.

To guarantee accuracy, the output pulse of the control chip

is trimmed to within 5% of 250 ns with nominal values of RT

and CT.

The outputs of the Oscillator and One−Shot comparators

are OR’d together to produce the pulse tOS, which drives the

Flip−Flop and output drivers. The output pulse (tOS) is

initiated by the Oscillator and terminated by the One−Shot

comparator. With zero voltage resonant mode converters,

the oscillator discharge time should never be set less than the

one−shot period.

Error Amplifier

A fully accessible high performance Error Amplifier is

provided for feedback control of the power supply system.

The Error Amplifier is internally compensated and features

dc open loop gain greater than 70 dB, input offset voltage of

less than 10 mV and a guaranteed minimum gain−bandwidth

product of 2.5 MHz. The input common mode range extends

from 1.5 V to 5.1 V, which includes the reference voltage.

Figure 17. Error Amplifier and Clamp

RVFO

Oscillator

Control Current

3.1 V

Error Amp Output

Noninverting Input

Inverting Input

Error

Amp

IOSC

7

8

6

3

Error Amp

Clamp

When the Error Amplifier output is coupled to the IOSC

pin by RVFO, as illustrated in Figure 17, it provides the

Oscillator Control Current, IOSC. The output swing of the

Error Amplifier is restricted by a clamp circuit to improve

its transient recovery time.

Output Section

The pulse(tOS), generated by the Oscillator and One−Shot

timer is gated to dual totem−pole output drives by the

Steering Flip−Flop shown in Figure 18. Positive transitions

of tOS toggle the Flip−Flop, which causes the pulses to

alternate between Output A and Output B. The flip−flop is

reset by the undervoltage lockout circuit during startup to

guarantee that the first pulse appears at Output A.

Figure 18. Steering Flip−Flop and Output Drivers

Output A

R

12

13

14

Output B

Power Ground

Q

T

Steering

Flip−Flop

PWR

GND

VCC

PWR

GND

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